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Digital Integrated Circuit Physical Design 1.2: Design Process

#IC#理论#物理设计12
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The document discusses three types of physical design methodologies in integrated circuit design: 1. **Flat Physical Design**: This approach involves designing from the bottom up using standard cells. It allows for comprehensive visibility of all cells, making global timing analysis and optimization easier. However, it has drawbacks such as high computational demands, challenges in resource allocation for large projects, longer design cycles, and inefficient resource utilization. 2. **Hierarchical Physical Design**: This method divides large designs into smaller blocks, allowing for independent layout and routing of each block. It focuses on complex timing modules and aims to shorten design convergence cycles by localizing timing issues. 3. **Silicon Virtual Prototyping**: This technique partitions the design during the layout phase and employs fast experimental routing methods. It uses lumped capacitance models for quick convergence assessments, with results typically within 5%-10% of the final design. In summary, flat design is suitable for small designs with global optimization but is resource-intensive. Hierarchical design is better for large designs, reducing complexity but limiting cross-module optimization. Silicon virtual prototyping supports rapid decision-making in early design stages through efficient modeling.

Flattened Physical Design#

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Flattened Physical Design: Physical design based on standard cells from bottom to top, including designing transistors, simulation, establishing layouts, and then simulating and modeling logic gate cells.

Advantages:#

  1. Comprehensive Information View: Flattened design allows designers to see information for all cells in the chip, which aids in global timing analysis and optimization.
  2. Easier Timing Convergence: Since the entire chip layout can be observed, timing convergence is relatively easier to handle, and any timing violations that occur are also relatively easier to resolve.
  3. Intuitiveness: For small designs, flattened design can be intuitively processed and optimized due to the smaller computational load.

Disadvantages:#

  1. High Computational Load: For large designs, flattened design requires handling a significant amount of computation, which may lead to substantial consumption of computational resources.
  2. Difficult Personnel Allocation: In large projects, it is challenging to effectively allocate personnel and fully utilize resources in flattened design, which may extend the design cycle.
  3. Long Design Cycle: Due to the high computational load and personnel allocation issues, flattened design may lead to a longer overall chip design cycle, affecting the time to market for the chip.
  4. Inefficient Resource Utilization: In large designs, flattened design struggles to fully utilize all available resources, which may lead to inefficiencies.

Overall, flattened physical design has its advantages when handling small or timing-critical designs, but its disadvantages become apparent when facing large and complex integrated circuit designs, especially in terms of computational resource consumption and design cycle.

Hierarchical Physical Design#

Hierarchical physical design divides the large design into several partitioned blocks during physical design, performing independent layout and routing for each partitioned block, and completing assembly design at the top level. This method focuses on handling timing-complex modules, shortening the design convergence cycle, and localizing timing issues.

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Silicon Virtual Prototype Design#

This method considers partitioning the entire design during the layout phase and uses fast approximate experimental routing methods during routing. When performing RC extraction, a lumped capacitance model can be used for quick design convergence evaluation, with a discrepancy of about 5%-10% from the final results.

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Summary#

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Flattened Physical Design: Bottom-up, intuitive and accurate, but with a long cycle. Suitable for small-scale designs, achieving global optimization but with high resource demands.
Hierarchical Physical Design: Top-down, block partitioning, localizing timing issues. Suitable for large-scale designs, reducing complexity through modularization, but with limited cross-module optimization.
Silicon Virtual Prototype Design: Fast, using experimental routing methods during routing. Used in early design stages, assessing physical implementation effects through efficient modeling, supporting rapid decision-making for complex chips.

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