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IC基础概念：集成电路设计流程

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The article outlines the integrated circuit (IC) design flow, which is a systematic approach involving several key steps to prepare the IC blueprint for manufacturing in a semiconductor factory. The typical IC design cycle includes: 1. **Specification and Architectural Design**: Defining the purpose, functions, speed, power consumption, and cost of the IC. 2. **Design Entry – Logic/Circuit Design**: Engineers implement logic functions using RTL and convert them to a gate-level netlist. 3. **Physical Design**: Transforming the logical representation into a manufacturable physical layout, adhering to design constraints like area, power, and timing. 4. **Physical Verification**: A repetitive process ensuring design correctness and robustness through various techniques to simulate physical effects and detect defects. 5. **Signoff**: Confirming and approving the chip design at various stages to ensure it meets specifications and performance metrics. This includes pre-layout functional simulation and post-layout timing simulation. The article emphasizes the importance of thorough signoff analysis to maintain IC product quality and reduce costs associated with issues found during production. Ultimately, the validated design data is sent to a semiconductor foundry for manufacturing.

Preface#

本文前情提要：

  • only focus on major/key steps in digital IC design flow.
  • 尽量避免晦涩术语

What is IC Design Flow#

集成电路设计流程是一种系统化的方法，包括一系列步骤，直至集成电路蓝图准备就绪，可以转移到半导体工厂进行制造。

Key Steps in IC Design Flow#

典型的 IC 设计周期包括几个步骤：

image.png
以下 flow 引用自 wiki:

  1. System specification
    1. Feasibility study and die size estimate
    2. Function analysis
  2. Architectural or system-level design
  3. Logic design
    1. Analogue design, simulation, and layout
    2. Digital design and simulation
    3. System simulation, emulation, and verification
  4. Circuit design
    1. Digital design synthesis
    2. Design for testing and automatic test pattern generation
    3. Design for manufacturability
  5. Physical design
    1. Floorplanning
    2. Place and route
    3. Parasitic extraction
  6. Physical verification and signoff
    1. Static timing
    2. Co-simulation and timing
  7. Mask data preparation (layout post-processing)
    1. Chip finishing with tape out
    2. Reticle layout
    3. Layout-to-mask preparation
  8. Reticle fabrication
  9. Photomask fabrication
  10. Wafer fabrication
  11. Packaging
  12. Die test
    1. Post silicon validation and integration
    2. Device characterization
    3. Tweak (if necessary)
  13. Chip deployment
    1. Datasheet generation (usually a PDF file)
    2. Ramp up
    3. Production
    4. Yield analysis / warranty analysis reliability
    5. Failure analysis on any returns
    6. Plan for next generation chip using production information if possible

再进一步总结为如下几个关键步骤

Specification and Architectural Design#

In this stage, design engineers should be able to answer these questions:

  • What is the IC made for?
  • What functions must the IC deliver? 
  • What is the required speed and power consumption? 
  • What is the target cost?

通俗来说此阶段即为高层次的顶层架构设计。

Design Entry – Logic/Circuit Design#

image.png

完成架构设计并确定要实现哪些功能后，工程师使用 RTL 实现逻辑功能，并通过逻辑综合完成 RTL to gate level Netlist 的转换。一般称逻辑设计为 IC 前端，物理设计为 IC 后端，逻辑综合为桥梁，提供物理设计所需的 Tech-dependent netlist.

Physical Design#

image.png

物理设计阶段的重点是将电路的逻辑表示转化为适合制造的物理布局。这涉及到 floor planning, placement, routing 等步骤，需要遵守严格的设计约束条件，如面积、功率和时序等要求，以满足 PPA.

Physical Verification#

image.png

物理验证阶段一个反复进行的过程，对确保设计的正确性和稳健性至关重要。采用包括模拟、形式验证和仿真在内的各种技术来模拟集成电路的物理效应（电阻、串扰等），检测设计缺陷，确保符合特定要求。

换句话说，这一阶段可以帮助设计人员想象电路将如何铺设在硅片上，并测量电路在压力下的功能。

Signoff (DFM – DFT and fabrication)#

signoff 指的是在设计流程的不同阶段对芯片进行确认和批准。通常，signoff 涉及到多个阶段和多个方面的确认，以确保设计在满足规格要求的情况下能够正常工作，并且符合预期的性能指标。

  1. 前仿真（功能仿真）    

在设计的电路进入布局布线前应检查其功能是否符合设计要求，这一仿真验证称之为第一次 sign-off。

  1. 后仿真（时序仿真）

设计经过布局布线之后，使用 EDA 工具进行寄生参数提取，形成精确的 post-layout 电路网表，对此网表做时序仿真，来检查时序行为是否符合要求，这一过程称之为第二次 sign-off。之后就可以进入 foundry 流片生产了。

Sign-off 分析做的是否完整和完备对 IC 产品的质量是至关重要的，若在这个阶段查找到问题并加以修正要比在生产阶段的花费要低廉很多，所以各个 IC 公司都非常重视这个过程，EDA 厂商也都有自己完整的用来做 sign-off 的工具集。

比较合适的方式是将 sign-off 分析集成到 IC 设计的流程中，与主体的设计工作形成一个迭代，以保证设计的质量。sign-off 阶段需要检查的 check-list 包含：时序、信号完整性、功耗、IR 降、电迁移、寄生参数提取、DRC（设计规则检查）、LVS（版图与电路图一致性检查）、噪声、片上热量分析等。这些项目的检查分析，可以在一个集成的环境中完成，如 Virtusos 或 Customer Designer。有些人把它称为 in-house sign-off.

总的来说：
芯片 tapeout 前会利用工具做各种检查。只有这些检查通过了，我们的芯片才有可能顺利流片，然后再将设计送交 fab 制造。所有会影响芯片性能或可制造性的关键参数都要根据 "golden signoff" 质量工具（包括 DFM 和 DFT）的结果进行验证。

  • DFM: design for manufacture
  • DFT: design for test

image.png

验证完成后，最终设计数据将被送到半导体代工厂进行制造。设计文件以及代工厂特定的指导方针和要求将被发送到半导体工厂。一旦设计完成，半导体制造流程就开始了，包括晶圆加工、光刻、蚀刻和封装，将硅晶圆转化为集成电路。

总结#

粗略地说，数字集成电路设计可分为三个部分。

  • Electronic system-level design: This step creates the user functional specification. The user may use a variety of languages and tools to create this description. Examples include a C/C++ model, VHDL, SystemC, SystemVerilog Transaction Level Models, Simulink, and MATLAB.
  • RTL design: This step converts the user specification (what the user wants the chip to do) into a register transfer level (RTL) description. The RTL describes the exact behavior of the digital circuits on the chip, as well as the interconnections to inputs and outputs.
  • Physical circuit design: This step takes the RTL, and a library of available logic gates (standard cell library), and creates a chip design. This step involves use of IC layout editor, layout and floor planning, figuring out which gates to use, defining places for them, and wiring (clock timing synthesis, routing) them together. ⭐

Note: RTL 负责让芯片做正确的事情。而 PD 完全不影响功能（如果设计正确的话），但决定了芯片的运行速度和成本。

Refs#

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