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Physical Design of Digital Integrated Circuits 3.1: Layout Planning

#IC#物理设计#理论31
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The document provides an overview of floorplan design in chip design, emphasizing its importance in optimizing chip performance, area, and power distribution. Key components of floorplan include: 1. **Chip Size (ifp)**: Establishes constraints and area for the chip. 2. **Chip I/O (ppl, pad)**: Involves pin placement to minimize wire lengths and connections via IO rings or bump arrays. 3. **Macro Placement (mpl, mpl2)**: Places macros while respecting design constraints. 4. **Power Distribution Network (pdn)**: Generates power grid strategies for the design. Floorplan impacts timing convergence, routing efficiency, power stability, and yield, typically occupying about one-third of the physical implementation time. Key terms include: - **Bond Pad**: Critical for electrical connections between the chip and packaging. - **Bump Array**: Essential for connections between the chip and substrate, especially in flip-chip and 3D IC packaging. The goals of floorplan include optimizing area, ensuring timing convergence, maintaining power stability, and improving routing efficiency. Before floorplan implementation, delay analysis is performed using a zero-load model to assess timing. The design approach can be either a bottom-up flattening method or a top-down hierarchical method, with the latter being preferred for larger designs (around 5 million gates). In hierarchical design, the process involves top-level planning, partitioning submodules, and assembling the chip. Timing budgeting is crucial, requiring analysis of the entire chip's timing. Module placement is influenced by the initial floorplan, and routing channels are designated spaces for wiring, ensuring that standard cells do not interfere with signal paths. Channels can be T or L-shaped, and feedthrough channels may be defined for larger module spans. The document also discusses routing methods, including channel-less designs.

Introduction#

Simple Summary#

A rough overview of floorplan in OpenROAD:

  1. The content of the floorplan is a complete planning and design of the internal interfaces of the chip, including:
    1. Chip size (ifp):
      1. initializes floorplan constraints, die/core area, and makes tracks.
    2. Chip IO (ppl, pad)
      1. pin placement: Place pins on the boundary of the die on the track grid to minimize net wirelengths.
      2. Chip-level Connections: either place an IO ring around the boundary of the chip and connect with either wirebond pads or a bump array.
    3. Macro placement (mpl, mpl2)
      1. The macro placer places macros/blocks honoring halos, channels, and cell row “snapping”.
    4. Power planning (pdn)
      1. PDN Generation: Specifies a small set of power grid strategies applied to the design, such as the number of layers, stripe width, and spacing, and then lets the utility generate the actual metal strips.
  2. The floorplan relates to the chip's timing convergence, routing smoothness, power stability, and yield.
  3. From floorplan to completed placement generally takes up 1/3 of the entire physical implementation time.

Terminology#

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  • Bond Pad is a critical contact point for electrical connection between the chip and the external package, ensuring the transmission of electrical signals and power distribution. Its layout directly affects the packaging process, signal integrity, and chip size, making it an important aspect of floorplan design.
  • Bump Array is a key structure for electrical, mechanical, and thermal connections between the chip and the package substrate or PCB, widely used in Flip-Chip and 3D IC packaging. The floorplan phase requires precise planning of the Bump Array's position, density, and distribution to optimize signal performance, power integrity, and thermal management.

Content and Objectives of Floorplan Planning#

The floorplan is the first step in chip physical design, used to determine the locations of the core area, macro units, IO units, as well as routing resources and power planning, to optimize chip performance and area.

The main objectives of the floorplan include:

  1. Area: Ensure routing while minimizing production costs.
  2. Timing Convergence: Estimate chip delay and consider whether it can ultimately meet SDC requirements to achieve timing convergence.
  3. Stability: Ensure uniform power distribution within the chip and sufficient power supply.
  4. Routing Efficiency: While ensuring smooth routing, minimize the length of the routing paths, thereby reducing interconnect delays and effectively improving chip performance.

Placement and Power Supply of I/O Interface Units#

  • TODO

Floorplan Planning Scheme and Delay Estimation#

Before performing the floorplan, delay analysis is conducted on the synthesized netlist using a zero-load model to evaluate timing. If the timing is poor, the netlist should be optimized.

The timing and delay estimation methods during the floorplan phase depend on the chip design methodology, namely 1. bottom-up flattening (flatten) silicon virtual prototyping (SVP); 2. top-down hierarchical design.

PS: When the design is around 5 million gates, consider adopting a hierarchical design scheme.

Flattened Design#

In flattened design, after placing multiple floorplans, STA is used to estimate the delay of the entire chip, and then timing violations (negative slack) are used to evaluate the effects of different floorplans.

Since interconnects have not yet been established at this stage, only WLM can be used to estimate delay (the term "only" is questionable, as WLM is a statistical model that estimates load capacitance and line length to initially predict line delay).

WLM (Wire Load Model) is a model used in the early stages of the RTL-to-GDSII flow (such as the synthesis stage) to estimate signal net capacitance, resistance, and delay, primarily based on circuit scale, net fanout, and statistical data.

Hierarchical Design#

Hierarchical design can be roughly divided into three steps: top-level chip design planning, sub-module partitioning and implementation, and top-level chip assembly implementation.

image.png

In timing budgeting, the timing of the entire chip needs to be analyzed first.

  • TODO

Module Placement and Routing Channels#

Module placement is based on floorplan planning, and the results of module layout will directly impact the expected goals of the earlier floorplan, where the completion of routing is assessed through routing channel analysis.

A routing channel is the space between two or more tracks, standard cells cannot be placed on the channel. Additionally, a halo is usually reserved around macros where standard cells are not allowed to be placed (for dedicated routing).

  • Routing Channel: The reserved routing channel space in the layout, typically found in gaps between macro units or cells.
  • Routing Track: The regular grid lines on the routing layer, with each track representing a position where signal lines can be placed.

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In hierarchical design, channels are categorized into T and L shapes based on their form. When two sub-modules are widely spaced, a feedthrough channel must also be defined to meet timing and routing requirements.

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A row-based routing method is introduced in hierarchical design, specifically the channel-less partitioning method shown in diagram b. Diagram a shows channel-based partitioning, while diagram c illustrates a hybrid method.

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